1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to apparatus method and for polishing one or both sides of a semiconductor wafer.
2. Description of the Related Art
Modem integrated circuits routinely incorporate hundreds of thousands or millions of active devices on a single substrate. Early in the fabrication flow of such circuits, each of the active devices is normally electrically isolated from other active devices. However, in the latter stages of a typical process flow, many of the active devices must be electrically interconnected to implement the desired circuit function for the integrated circuit. In early integrated circuits incorporating a few hundred or thousand devices, the interconnection of the devices was routinely accomplished via a single interconnect layer. However, modem integrated circuits almost invariably require more than one level of interconnect, and often four or more. Without them, many modem integrated circuits would otherwise require much larger chip areas, and often long distance interconnect paths, resulting in large RC products and unacceptably large propagation delays.
The introduction of multi-level interconnect structures introduced a new set of problems related to topography. An interlevel dielectric layer is normally required between each interconnect level. As the number of conductor and interlevel dielectric layers in a given technology is increased, the stacking of these additional layers on top of one another produces a more and more rugged topography. Without suitable planarization of the interlevel dielectric layers, microscopic canyons can form, creating topography conditions that may eventually reduce the yield of circuits to an unacceptable level. Some of these undesirable conditions include poor step coverage of conductor lines, conductor stringers left behind following anisotropic etching, and an artificial degradation of the maximum resolution of a given photolithographic patterning tool. If the topography of a given layer of an integrated circuit includes steps that are larger than a particular maximum value, it may not be possible to pattern features in the layer to the maximum resolution of the particular optical lithography tool.
Planarization of interlevel dielectrics became commonplace early in multi-level interconnect processing. In more recent years, planarization techniques have also become an important component of other phases of semiconductor fabrication. For example, shallow trench isolation structures are commonly fabricated by forming a trench network in a substrate and blanketing the substrate with a trench isolation material. The blanket layer of trench isolation material is then planarized down to the substrate, leaving only the preformed trenches filled with the isolation material. Similarly, local interconnect structures of tungsten or polysilicon are routinely planarized in more modem processes.
Etchback planarization has been a widely used planarization technique for a number of years. In etchback planarization processing, the interlevel dielectric layer is etched back to a desired final thickness, commonly by plasma or reactive ion etching. In some processes, the etchback is carried out through the use of a sacrificial layer that is deposited on the interlevel dielectric layer prior to the etchback. Barrier masks are often incorporated beneath the sacrificial layer. Tight process control is necessary for parameters such as the magnitude of the etch rate, the etch rate uniformity across the wafer, and endpoint detection in order to achieve a desired degree of planarity and final dielectric film thickness using etchback planarization. Adequate process control of all three of these and other parameters may prove elusive and result in poor yields.
Chemical-mechanical-polishing ("CMP") has augmented, and in many cases supplanted etchback planarization as a dominant planarization technique in integrated circuit processing. In conventional CMP processing, a wafer surface is lapped with the aid of a chemical slurry that consists of particulates of an abrasive dispersed in a liquid solvent. The slurry often includes a material that will chemically react with the wafer surface to form a compound that is more readily abraded than the original surface material. For example, a slurry used to polish SiO.sub.2 may contain aluminum oxide particles that react with the SiO.sub.2 to form aluminum silicate, which is more easily abraded than SiO.sub.2.
Many conventional CMP machines include a flat, round, rotating polishing disk or pad that is disposed in a flat or horizontal orientation and is designed to polish several wafers simultaneously. The pad is often quite large, e.g., 36 inches in diameter or more, and is commonly made from a compliant material such as rubber. The wafers are secured to a horizontally disposed carrier via vacuum chucks. The carrier is lowered until the wafers contact the rotating polishing pad. A polishing slurry is interspersed between the wafer surface and the polishing pad. Acceptable planarity is highly dependent on uniform slurry dispersal.
There are several disadvantages associated with conventional CMP apparatus and processing. In CMP machines where the wafer is secured to a carrier by vacuum, excess vacuum force applied near the center of the wafer can lead to a phenomenon known as "dishing" where the wafer deforms slightly and takes on a dish-like profile. The problem may also arise, or be amplified where the wafer is not uniformly supported by the carrier, and as a result, undergoes deflection during polishing. In either case, poor planarity across the wafer surface may result.
Another source of nonuniform planarization is introduced by the nature of conventional compliant polish pads. Despite careful molding and shaping, nearly all new compliant polish pads have random variations in surface profile across their polish surfaces. Repeated use of the pad introduces additional variations into these polishing surfaces as a result of wear caused by the abrasive environment. These variations translate into undesirable variations in planarity of a polished wafer surface. To compensate for the anticipated variations in pad surface profile, many conventional machines deliberately introduce vibrations into the wafer. The goal is to attempt to cancel out the effects of the random nonuniformities by rapidly varying the pressure on the wafer. However, the vibration technique may not completely compensate for pad nonuniformity and may itself introduce additional variations in planarity across a given wafer. Another solution is to discard the pad after a set number of wafers. In many systems, the pad is replaced after every one hundred (100) wafers. This technique involves maintenance cost and downtime.
Inadequate slurry dispersion is another drawback associated with conventional CMP machines. As noted above, uniform dispersion of polishing slurry across the wafer surface is a key factor in achieving uniform planarity. However, many polishing slurries have relatively high viscosities and do not flow easily across a horizontal surface, particularly a large one such as a conventional polish pad. Dispersion may be nonuniform and planarity may, in turn, be less than desired. To compensate for the otherwise poor flow characteristics of the slurry, the carrier is manipulated to increase the force pressing the wafers against the polish pad to levels that improve dispersion. In some systems, the force required may be 16 to 32 pounds or more. However, the high loading may amplify the effects of surface variations in the polish pad.
Another disadvantage associated with conventional CMP processing is the inability to efficiently polish both sides of a dual sided wafer. Conventional machines are configured to polish one side of a given wafer at a time. If polishing of both sides of a dual sided wafer is contemplated, one side of the wafer must first be polished in the machine, and then the wafer must be dropped from the carrier, flipped and repositioned in the carrier, and subjected to a second polishing operation. This may be a time consuming operation and requires very delicate handling of the wafer to avoid damaging the polished side while the unpolished side is processed.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.